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RT8167A ? ds8167a-00 january 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dual single-phase pwm controller for cpu core/gfx power supply features z z z z z g-navp tm (green native active voltage positioning) topology z z z z z dual output controller with two built-in gate drivers z z z z z serial vid interface z z z z z 0.5% dac accuracy z z z z z differential remote output voltage sensing z z z z z built-in adc for platform programming z z z z z diode emulation mode (dem) at light load condition z z z z z droop enable/disable z z z z z fast transient response z z z z z vr12/imvp7 compatible power management states z z z z z vr ready indicator z z z z z thermal throttling indicator z z z z z current monitor output z z z z z switching frequency up to 1mhz per phase z z z z z protection : ovp, uvp, nvp, ocp, uvlo z z z z z small 48-lead wqfn package z z z z z rohs compliant and halogen free applications z vr12 / imvp7 intel cpu core supply z avp step-down converter z notebook/ netbook/ desktop computer cpu core supply ordering information note : richtek products are : ` rohs compliant and compatible with the current requirements of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. general description the RT8167A is a dual single-phase synchronous buck pwm controller with integrated gate drivers, compliant with intel vr12/imvp7 specification. a serial vid (svid) interface is built-in in the RT8167A to communicate with intel vr12/imvp7 compliant cpu. the integrated differential remote output voltage sensing function and built-in high accuracy dac achieve accurate output voltage regulation. the RT8167A supports vr12/ imvp7 compatible power management states and vid on-the-fly function. the RT8167A operates in two power management states including dem in ps2 and forced-ccm in ps1/ps0. richtek ' s proprietary g-navp tm (green native avp) makes avp (active voltage positioning) design easier and more robust. by utilizing the g-navp tm topology, dem and ccm efficiency can be improved. the RT8167A integrates high accuracy adc for platform setting functions, such as no-load offset or over current level. individual vr ready output signals are provided for both core vr and gfx vr. the ic also features complete fault protection functions, including over voltage, under voltage, negative voltage, over current and under voltage lockout. the RT8167A is available in a wqfn-48l 6x6 small foot print package. marking information RT8167Agqw : product number ymdnn : date code package type qw : wqfn-48l 6x6 (w-type) RT8167A lead plating system g : green (halogen free and pb free) RT8167A gqw ymdnn
RT8167A ? ds8167a-00 january 2012 www.richtek.com 2 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 isen1p positive current sense input of core vr 2 isen1n negative current sense input of core vr 3 comp core vr compensation. this pin is the output node of the error amplifier. 4 fb core vr feedback. this is the negative input node of the error amplifier. 5 rgnd return ground for core vr. this pin is the negative input for differential remote voltage sensing. 6 imon current monitor output of core vr. the output voltage v imon of this pin is proportional to the output current. for digital output current reporting, detailed v imon is generated by built-in adc. 7 imonfb this pin is used to externally set the current monitor output gain of core vr. connect this pin with one resistor r imonfb to core vcc_sense while imon pin is connected to ground with another resistor, r imon . the current monitor output gain can be set by the ratio of these two resistors. 8 drpen droop enable mode setting of core vr. an internal 80 a current source is connected to the drpen pin and flows out of this pin for 10 s. connect this pin to v cc to enable droop function. connect this pin to gnd to disable droop function. 9 ofs output voltage no-load offset setting of core vr. connect to a resistive voltage divider from v cc to gnd to set the pin voltage v ofs for offset setting. connect this pin to gnd for no offset setting. 10 ofsa output voltage no-load offset setting of gfx vr. connect to a resistive voltage divider from v cc to gnd to set the pin voltage v ofs a for offset setting. connect this pin to gnd for no offset setting. pin configurations wqfn-48l 6x6 (top view) isen1p fb comp vcc gfxps2 ofsa ofs drpen imonfb rgnd imon isen1n setinia setini tmpmax iccmax iccmaxa tsen vr_ready ocset tsena ocseta ibias isenap fba compa vra_ready drpena vdio vclk imonfba rgnda imona isenan tonset boot ugate phase lgate pvcc tonseta lgatea phasea ugatea boota en gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 49 vrhot alert
RT8167A ? ds8167a-00 january 2012 www.richtek.com 3 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. pin name pin function 11 gfxps2 forced dem enable setting of gfx vr. connect to v cc for forced-dem setting and connect to gnd for following svid power state command. 12 vcc 5v power supply input of controller. bypass this pin to gnd with a 1 f or greater ceramic capacitor. 13 setinia initial startup voltage v ini_gfx setting of gfx vr. connect to a resistive voltage divider from v cc to gnd to set the pin voltage v setinia for gfx vr initial startup voltage v in i_gfx setting. connect this pin to gnd for 0v v in i_gfx setting. 14 setini initial startup voltage v ini_core setting of core vr. connect to a resistive voltage divider from v cc to gnd to set the pin voltage v setini for core vr initial startup voltage v ini_core setting. connect this pin to gnd for 0v v ini_core setting. 15 tmpmax maximum temperature setting of core vr. connect to a resistive voltage divider from v cc to gnd to set the pin voltage v tm pm ax for tmpmax setting. 16 iccmax maximum current setting of core vr. connect to a resistive voltage divider from v cc to gnd to set the pin voltage v iccmax for iccmax setting. 17 iccmaxa maximum current setting of gfx vr. connect to a resistive voltage divider from v cc to gnd to set the pin voltage v iccmaxa for iccmaxa setting. 18 tsen thermal monitor sense pin of core vr. 19 ocset over current protection setting of core vr. connect to a resistive voltage divider from v cc to gnd to set the pin voltage v ocset from 0 to 3.3v for core vr over current protection threshold. 20 tsena thermal monitor sense pin of gfx vr. 21 ocseta over current protection setting of gfx vr. connect to a resistive voltage divider from v cc to gnd to adjust the pin voltage v ocseta from 0 to 3.3v for gfx vr over current protection threshold. 22 ibias internal bias current setting. connect a 53.6k resistor from ibias pin to gnd. 23 vrhot thermal monitor output (active low). connect a pull high resistor from vrhot pin to 1.05v. 24 vr_ready voltage ready indicator of core vr. connect a pull high resistor from vr_ready pin to 1.05v. 25 vra_ready voltage ready indicator gfx vr. connect a pull high resistor from vra_ready pin to 1.05v. 26 drpena droop enable mode setting of gfx vr. an internal 80 a current source is connected to drpena pin and flows out of this pin for 10 s. connect this pin to v cc to enable droop function. connect this pin to gnd to disable droop function. 27 alert svid alert pin (active low). connect a 75 resistor from alert pin to 1.05v. 28 vdio controller and cpu data transmission interface. connecting a 64.9 resistor between vdio pin to 1.05v. 29 vclk synchronous clock from the cpu. connect a 64.9 resistor from vclk pin to 1.05v. 30 imonfba this pin is used to externally set the current monitor output gain of gfx vr. connect this pin with one resistor r imonfba to gfx vcc_sense while imon pin is connected to ground with another resistor r imon a . the current monitor output gain can be set by the ratio of these two resistors. 31 imona current monitor output of gfx vr. the output voltage vimona of this pin is proportional to the output current. for digital output current reporting, detailed vimona is generated by built-in adc.
RT8167A 4 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. pin name pin function 32 rgnda return ground for gfx vr. this pin is the negative input for differential remote voltage sensing. 33 fba gfx vr feedback. this is the negative input node of the error amplifier. 34 compa gfx vr compensation. this pin is the output node of the error amplifier. 35 isenan negative current sense input of gfx vr. 36 isenap positive current sense input of gfx vr. 37 tonseta on-time setting of gfx vr. connect this pin to vin with one resistor. 38 en chip enable (active high). 39 boota bootstrap flying capacitor connection for gfx vr. this pin powers the high side mosfet drivers. connect this pin to phasea with an external ceramic capacitor. 40 ugatea high side mosfet floating gate driver output for gfx vr. connect this pin to the gate of high side mosfet. 41 phasea switching node connection for gfx vr. phasea is also the zero cross detect input for gfx vr. connect this pin to the high side mosfet sources together with the low side mosfet drains and the inductor. 42 lgatea synchronous-rectifier gate driver output of gfx vr. connect this pin to the gate of low side mosfet. 43 pvcc 5v power supply of driver. bypass this pin to gnd with a 1 f or greater ceramic capacitor. 44 lgate synchronous-rectifier gate driver output of core vr. connect this pin to the gate of low side mosfet. 45 phase switching node connection for core vr. phase is the internal lower supply rail for the ugate. phase is also the zero cross detect input for core vr. connect this pin to the high side mosfet sources together with the low side mosfet drains and the inductor. 46 ugate high side mosfet floating gate driver output for core vr. connect this pin to the gate of high side mosfet. 47 boot bootstrap flying capacitor connection for core vr. this pin powers the high side mosfet drivers. connect this pin to phase with an external ceramic capacitor. 48 tonset on-time setting of core vr. connect this pin to vin with one resistor. 49 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
RT8167A 5 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit figure 1. dual output application circuit ? = 3 3 8 0 ? = 3 3 8 0 v c c 2 1 c 1 9 g n d 4 9 ( e x p o s e d p a d ) 4 5 p h a s e v d i o 3 8 e n e n i b i a s 2 2 r 6 4 r59 r58 t s e n a t s e n 1 8 2 0 v c c r 6 2 r 6 3 1 0 o f s a 1 1 g f x p s 2 v c c 1 5 1 6 i c c m a x r 3 7 r 3 8 r 3 9 i c c m a x a 1 7 r 4 7 r 4 8 r 4 9 t m p m a x i c c m a x i c c m a x a t m p m a x o f s 9 r 4 0 r 5 0 r 4 1 o f s a o f s r 5 1 r 4 2 r 5 2 g f x p s 2 2 6 d r p e n a 8 d r p e n o c s e t a r 1 9 r 1 8 r 1 7 1 9 1 3 s e t i n i a r 2 0 r 2 1 r 2 2 s e t i n i 1 4 r 3 1 r 3 2 r 3 3 r 3 0 r 2 9 r 2 8 o c s e t d r p e n a d r p e n o c s e t a s e t i n i a s e t i n i o c s e t 2 9 v c l k 2 8 v d i o 2 7 2 5 v r a _ r e a d y 2 4 v r _ r e a d y 2 3 a l e r t v r h o t v c l k a l e r t r8 r7 r6 v c c p v r a _ r e a d y v r _ r e a d y r9 r10 r11 v r h o t r t 8 1 6 7 a v c c c 1 1 2 r 1 5 v v c c 4 6 4 8 t o n s e t 4 7 l 1 v i n c 4 c 3 q 1 r 4 r 5 5 v t o 2 5 v r 2 c 2 r 3 b o o t u g a t e v c o r e c 6 4 4 i s e n 1 n i s e n 1 p 1 r 1 4 r 1 3 c 7 f b c 1 2 c 1 1 i m o n f b r 2 3 c 9 p v c c c 8 4 3 7 4 2 q 2 r 1 2 r n t c 1 r 1 5 r 1 6 5 v l g a t e c 1 0 r 2 4 imon c 1 3 r 3 5 r 3 4 r 3 6 3 7 t o n s e t a v i n r 4 3 c 1 4 r 4 4 r n t c a v g f x 4 0 u g a t e a l g a t e a 3 9 b o t t a p h a s e a c 1 6 c 1 5 q 3 r 4 5 r 4 6 i s e n a n i s e n a p 3 6 3 5 f b a c 2 3 c 2 2 i m o n f b a c 2 0 3 0 3 3 r 6 0 r 6 1 c 2 1 g f x v c c _ s e n s e r 6 8 g f x v s s _ s e n s e v g f x r 6 5 r 6 7 3 2 r 6 6 i m o n a c 2 4 r 6 9 r 7 0 3 1 i m o n a c o m p a 3 4 r g n d a 4 1 4 2 l 2 r 5 5 r 5 4 c 1 7 q 4 r 5 3 c o m p r 2 5 core vcc_ sense r 2 7 3 r g n d 5 r 2 6 v core core vss_sense 6 i m o n o p t i o n a l c 5 optional optional o p t i o n a l r 5 6 r 5 7 c 1 8 o p t i o n a l c 2 5 2 . 2 1 f 130 130 150 10k 10k 75 1 0 k 1 0 k 8 . 7 k 2 7 k 1 0 k 1 0 k n c 1 0 k 1 0 k n c n c n c n c n c n c 1 0 0 k 1 5 0 k 5 1 k 1 0 k 0 0 1 . 6 k 5 . 1 k 3 3 k 1 0 k 1 2 k 10k 12k r 7 2 7 5 0 r 7 1 7 5 0 1 k 1 k 5 3 . 6 k 1 3 0 k 5 . 1 0 . 1 f 0 0 0 . 1 f 1 0 f 0 1 h 4 . 7 k o p t i o n a l 1 f 3 . 9 k c 2 6 3 3 0 f / 9 m 3 3 0 f / 9 m 4 . 7 k 2 . 4 k 0 . 0 6 8 f 10k 0 o p t i o n a l optional 7 1 k 1 0 k 1 0 0 100 6 2 0 k 3 9 k 0 . 1 f 0 . 1 f 0 . 1 f 0 0 0 1 0 f 2 h 5 v t o 2 5 o p t i o n a l 1 k c 2 7 3 3 0 f / 1 5 m 3 3 0 f / 1 5 m 1 1 k 1 . 2 k 1 k 0 . 1 f 0 1 0 k o p t i o n a l o p t i o n a l 1 0 0 4 2 k 1 0 k 1 0 0 1 8 0 k 1 . 8 m 0 . 1 f r n t c t a r n t c t 1 d c r 7 . 6 m d c r 1 4 . 6 m
RT8167A 6 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 2. single output application circuit c2 0.1f vcc 1 2 5 v v c c ofsa 2 9 vclk v c l k 2 8 vdio v d i o 2 7 a l e r t v c c p 2 4 vr_ready v r _ r e a d y v r h o t 2 3 alert vrhot v core c6 c8 1f q 2 r11 0 5v r 1 2 c 7 l1 c4 10f c3 0.1f q 1 r4 0 r 5 0 v i n 5v to 25 r2 130k r3 5.1 RT8167A 4 8 tonset 4 6 4 5 4 4 isen1n 4 7 i s e n 1 p 1 p v c c 4 3 2 boot ugate phase l g a t e 6 imon comp f b imonfb 7 4 3 rgnd 5 1 0 4 0 4 1 4 2 3 7 3 9 3 6 3 1 3 0 3 3 3 4 3 5 3 2 2 5 1 3 1 7 2 0 1 1 2 1 2 6 v c c vcc gnd gnd floating floating floating floating gnd vcc gnd gnd floating floating vcc gnd vcc gnd vcc gnd ugatea lgatea tonseta boota phasea vra_ready g f x p s 2 i c c m a x a i s e n a n i s e n a p i m o n a c o m p a f b a i m o n f b a r g n d a setinia t s e n a o c s e t a drpena 3 8 en e n gnd 49 (exposed pad) ibias 2 2 r38 53.6k n t c t 1 1 0 k r 3 6 1 2 k tsen 1 8 v c c r37 1k iccmax tmpmax ofs v c c 1 5 1 6 r30 51k r31 150k r33 33k r34 5.1k i c c m a x t m p m a x 9 r32 nc o f s r35 0 8 drpen r16 10k v c c r17 8.7k r18 10k setini 1 4 r28 10k r29 nc r27 nc ocset d r p e n s e t i n i o c s e t c 9 r21 71k c 1 2 c 1 1 r 2 3 1 0 0 r19 10k r 2 2 1 0 k c 1 0 r20 0 i m o n c 1 3 0 . 1 f r24 c o r e v c c _ s e n s e r 2 6 r25 v c o r e c o r e v s s _ s e n s e 1 9 optional r14 4.7k r15 2.4k r13 3.9k r n t c 1 4 . 7 k optional r8 r7 r6 r9 r 1 0 130 130 150 10k 75 r1 2.2 c 1 1 f optional c25 r39 750 c5 0.068f 1h 330f /9m o p t i o n a l 330f /9m 620k 39k 100k optional optional c26 ? = 3 3 8 0 d c r 7 . 6 m
RT8167A 7 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram iccmaxa fb comp rgnd tsen isen1n isen1p ocset fba compa error amp gfx vr ocp gfx vr protection signal isenan iccmax tmpmax control & protection logic mux adc svid xcvr vdio vclk tonseta en isenap ocseta vr_ready vra_ready rgnda pwm cmp gfx vr vid/ofs control slew rate control vrefa vref vcc vref imonfb uvlo gfx vr ov/uv/nv ibias tonset gfx vr current monitor vrefa imonfba imona boot ugate phase lgate pvcc gfx vr ccrcot pwm generator boota ugatea phasea lgatea ofs setinia setini tsena drpena drpen imon ofsa droop enabler gfx 0ll en gfx 0ll en core 0ll en core vr current monitor gnd core vr ccrcot pwm generator droop enabler core 0ll en pvdd driver logic control dac ofs control offset cancellation gfx vr slew rate control error amp core vr vid/ofs control slew rate control + - 10 dac ofs control offset cancellation core vr slew rate control driver logic control gfx vr slew rate control core vr slew rate control gfx vr vid/ofs control core vr vid/ofs control gfx 0ll en core 0ll vcs gfx 0ll vcs core 0ll vcs core 0ll en gfx 0ll vcs core vr protection signal gfx vr protection signal core vr ocp core vr protection signal core vr ov/uv/nv 2.14v pwm cmp vrefa vref gm current sense amp current sense amp gm gfx vr operation mode core vr operation mode gfx vr operation mode core vr operation mode gfxps2 vrhot + - + - + - + - + - + - alert 10 + - x4.8 x4.8 /5 /5
RT8167A 8 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 h1 h0 vdac voltage 0 0 0 0 0 0 0 0 0 0 0.000 0 0 0 0 0 0 0 1 0 1 0.250 0 0 0 0 0 0 1 0 0 2 0.255 0 0 0 0 0 0 1 1 0 3 0.260 0 0 0 0 0 1 0 0 0 4 0.265 0 0 0 0 0 1 0 1 0 5 0.270 0 0 0 0 0 1 1 0 0 6 0.275 0 0 0 0 0 1 1 1 0 7 0.280 0 0 0 0 1 0 0 0 0 8 0.285 0 0 0 0 1 0 0 1 0 9 0.290 0 0 0 0 1 0 1 0 0 a 0.295 0 0 0 0 1 0 1 1 0 b 0.300 0 0 0 0 1 1 0 0 0 c 0.305 0 0 0 0 1 1 0 1 0 d 0.310 0 0 0 0 1 1 1 0 0 e 0.315 0 0 0 0 1 1 1 1 0 f 0.320 0 0 0 1 0 0 0 0 1 0 0.325 0 0 0 1 0 0 0 1 1 1 0.330 0 0 0 1 0 0 1 0 1 2 0.335 0 0 0 1 0 0 1 1 1 3 0.340 0 0 0 1 0 1 0 0 1 4 0.345 0 0 0 1 0 1 0 1 1 5 0.350 0 0 0 1 0 1 1 0 1 6 0.355 0 0 0 1 0 1 1 1 1 7 0.360 0 0 0 1 1 0 0 0 1 8 0.365 0 0 0 1 1 0 0 1 1 9 0.370 0 0 0 1 1 0 1 0 1 a 0.375 0 0 0 1 1 0 1 1 1 b 0.380 0 0 0 1 1 1 0 0 1 c 0.385 0 0 0 1 1 1 0 1 1 d 0.390 0 0 0 1 1 1 1 0 1 e 0.395 0 0 0 1 1 1 1 1 1 f 0.400 0 0 1 0 0 0 0 0 2 0 0.405 0 0 1 0 0 0 0 1 2 1 0.410 0 0 1 0 0 0 1 0 2 2 0.415 table 1. imvp7/vr12 compliant vid table
RT8167A 9 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 h1 h0 dac voltage 0 0 1 0 0 0 1 1 2 3 0.420 0 0 1 0 0 1 0 0 2 4 0.425 0 0 1 0 0 1 0 1 2 5 0.430 0 0 1 0 0 1 1 0 2 6 0.435 0 0 1 0 0 1 1 1 2 7 0.440 0 0 1 0 1 0 0 0 2 8 0.445 0 0 1 0 1 0 0 1 2 9 0.450 0 0 1 0 1 0 1 0 2 a 0.455 0 0 1 0 1 0 1 1 2 b 0.460 0 0 1 0 1 1 0 0 2 c 0.465 0 0 1 0 1 1 0 1 2 d 0.470 0 0 1 0 1 1 1 0 2 e 0.475 0 0 1 0 1 1 1 1 2 f 0.480 0 0 1 1 0 0 0 0 3 0 0.485 0 0 1 1 0 0 0 1 3 1 0.490 0 0 1 1 0 0 1 0 3 2 0.495 0 0 1 1 0 0 1 1 3 3 0.500 0 0 1 1 0 1 0 0 3 4 0.505 0 0 1 1 0 1 0 1 3 5 0.510 0 0 1 1 0 1 1 0 3 6 0.515 0 0 1 1 0 1 1 1 3 7 0.520 0 0 1 1 1 0 0 0 3 8 0.525 0 0 1 1 1 0 0 1 3 9 0.530 0 0 1 1 1 0 1 0 3 a 0.535 0 0 1 1 1 0 1 1 3 b 0.540 0 0 1 1 1 1 0 0 3 c 0.545 0 0 1 1 1 1 0 1 3 d 0.550 0 0 1 1 1 1 1 0 3 e 0.555 0 0 1 1 1 1 1 1 3 f 0.560 0 1 0 0 0 0 0 0 4 0 0.565 0 1 0 0 0 0 0 1 4 1 0.570 0 1 0 0 0 0 1 0 4 2 0.575 0 1 0 0 0 0 1 1 4 3 0.580 0 1 0 0 0 1 0 0 4 4 0.585 0 1 0 0 0 1 0 1 4 5 0.590
RT8167A 10 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 h1 h0 dac voltage 0 1 0 0 0 1 1 0 4 6 0.595 0 1 0 0 0 1 1 1 4 7 0.600 0 1 0 0 1 0 0 0 4 8 0.605 0 1 0 0 1 0 0 1 4 9 0.610 0 1 0 0 1 0 1 0 4 a 0.615 0 1 0 0 1 0 1 1 4 b 0.620 0 1 0 0 1 1 0 0 4 c 0.625 0 1 0 0 1 1 0 1 4 d 0.630 0 1 0 0 1 1 1 0 4 e 0.635 0 1 0 0 1 1 1 1 4 f 0.640 0 1 0 1 0 0 0 0 5 0 0.645 0 1 0 1 0 0 0 1 5 1 0.650 0 1 0 1 0 0 1 0 5 2 0.655 0 1 0 1 0 0 1 1 5 3 0.660 0 1 0 1 0 1 0 0 5 4 0.665 0 1 0 1 0 1 0 1 5 5 0.670 0 1 0 1 0 1 1 0 5 6 0.675 0 1 0 1 0 1 1 1 5 7 0.680 0 1 0 1 1 0 0 0 5 8 0.685 0 1 0 1 1 0 0 1 5 9 0.690 0 1 0 1 1 0 1 0 5 a 0.695 0 1 0 1 1 0 1 1 5 b 0.700 0 1 0 1 1 1 0 0 5 c 0.705 0 1 0 1 1 1 0 1 5 d 0.710 0 1 0 1 1 1 1 0 5 e 0.715 0 1 0 1 1 1 1 1 5 f 0.720 0 1 1 0 0 0 0 0 6 0 0.725 0 1 1 0 0 0 0 1 6 1 0.730 0 1 1 0 0 0 1 0 6 2 0.735 0 1 1 0 0 0 1 1 6 3 0.740 0 1 1 0 0 1 0 0 6 4 0.745 0 1 1 0 0 1 0 1 6 5 0.750 0 1 1 0 0 1 1 0 6 6 0.755 0 1 1 0 0 1 1 1 6 7 0.760 0 1 1 0 1 0 0 0 6 8 0.765 0 1 1 0 1 0 0 1 6 9 0.770
RT8167A 11 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 h1 h0 dac voltage 0 1 1 0 1 0 1 0 6 a 0.775 0 1 1 0 1 0 1 1 6 b 0.780 0 1 1 0 1 1 0 0 6 c 0.785 0 1 1 0 1 1 0 1 6 d 0.790 0 1 1 0 1 1 1 0 6 e 0.795 0 1 1 0 1 1 1 1 6 f 0.800 0 1 1 1 0 0 0 0 7 0 0.805 0 1 1 1 0 0 0 1 7 1 0.810 0 1 1 1 0 0 1 0 7 2 0.815 0 1 1 1 0 0 1 1 7 3 0.820 0 1 1 1 0 1 0 0 7 4 0.825 0 1 1 1 0 1 0 1 7 5 0.830 0 1 1 1 0 1 1 0 7 6 0.835 0 1 1 1 0 1 1 1 7 7 0.840 0 1 1 1 1 0 0 0 7 8 0.845 0 1 1 1 1 0 0 1 7 9 0.850 0 1 1 1 1 0 1 0 7 a 0.855 0 1 1 1 1 0 1 1 7 b 0.860 0 1 1 1 1 1 0 0 7 c 0.865 0 1 1 1 1 1 0 1 7 d 0.870 0 1 1 1 1 1 1 0 7 e 0.875 0 1 1 1 1 1 1 1 7 f 0.880 1 0 0 0 0 0 0 0 8 0 0.885 1 0 0 0 0 0 0 1 8 1 0.890 1 0 0 0 0 0 1 0 8 2 0.895 1 0 0 0 0 0 1 1 8 3 0.900 1 0 0 0 0 1 0 0 8 4 0.905 1 0 0 0 0 1 0 1 8 5 0.910 1 0 0 0 0 1 1 0 8 6 0.915 1 0 0 0 0 1 1 1 8 7 0.920 1 0 0 0 1 0 0 0 8 8 0.925 1 0 0 0 1 0 0 1 8 9 0.930 1 0 0 0 1 0 1 0 8 a 0.935 1 0 0 0 1 0 1 1 8 b 0.940 1 0 0 0 1 1 0 0 8 c 0.945 1 0 0 0 1 1 0 1 8 d 0.950
RT8167A 12 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 h1 h0 dac voltage 1 0 0 0 1 1 1 0 8 e 0.955 1 0 0 0 1 1 1 1 8 f 0.960 1 0 0 1 0 0 0 0 9 0 0.965 1 0 0 1 0 0 0 1 9 1 0.970 1 0 0 1 0 0 1 0 9 2 0.975 1 0 0 1 0 0 1 1 9 3 0.980 1 0 0 1 0 1 0 0 9 4 0.985 1 0 0 1 0 1 0 1 9 5 0.990 1 0 0 1 0 1 1 0 9 6 0.995 1 0 0 1 0 1 1 1 9 7 1.000 1 0 0 1 1 0 0 0 9 8 1.005 1 0 0 1 1 0 0 1 9 9 1.010 1 0 0 1 1 0 1 0 9 a 1.015 1 0 0 1 1 0 1 1 9 b 1.020 1 0 0 1 1 1 0 0 9 c 1.025 1 0 0 1 1 1 0 1 9 d 1.030 1 0 0 1 1 1 1 0 9 e 1.035 1 0 0 1 1 1 1 1 9 f 1.040 1 0 1 0 0 0 0 0 a 0 1.045 1 0 1 0 0 0 0 1 a 1 1.050 1 0 1 0 0 0 1 0 a 2 1.055 1 0 1 0 0 0 1 1 a 3 1.060 1 0 1 0 0 1 0 0 a 4 1.065 1 0 1 0 0 1 0 1 a 5 1.070 1 0 1 0 0 1 1 0 a 6 1.075 1 0 1 0 0 1 1 1 a 7 1.080 1 0 1 0 1 0 0 0 a 8 1.085 1 0 1 0 1 0 0 1 a 9 1.090 1 0 1 0 1 0 1 0 a a 1.095 1 0 1 0 1 0 1 1 a b 1.100 1 0 1 0 1 1 0 0 a c 1.105 1 0 1 0 1 1 0 1 a d 1.110 1 0 1 0 1 1 1 0 a e 1.115 1 0 1 0 1 1 1 1 a f 1.120 1 0 1 1 0 0 0 0 b 0 1.125 1 0 1 1 0 0 0 1 b 1 1.130
RT8167A 13 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 h1 h0 dac voltage 1 0 1 1 0 0 1 0 b 2 1.135 1 0 1 1 0 0 1 1 b 3 1.140 1 0 1 1 0 1 0 0 b 4 1.145 1 0 1 1 0 1 0 1 b 5 1.150 1 0 1 1 0 1 1 0 b 6 1.155 1 0 1 1 0 1 1 1 b 7 1.160 1 0 1 1 1 0 0 0 b 8 1.165 1 0 1 1 1 0 0 1 b 9 1.170 1 0 1 1 1 0 1 0 b a 1.175 1 0 1 1 1 0 1 1 b b 1.180 1 0 1 1 1 1 0 0 b c 1.185 1 0 1 1 1 1 0 1 b d 1.190 1 0 1 1 1 1 1 0 b e 1.195 1 0 1 1 1 1 1 1 b f 1.200 1 1 0 0 0 0 0 0 c 0 1.205 1 1 0 0 0 0 0 1 c 1 1.210 1 1 0 0 0 0 1 0 c 2 1.215 1 1 0 0 0 0 1 1 c 3 1.220 1 1 0 0 0 1 0 0 c 4 1.225 1 1 0 0 0 1 0 1 c 5 1.230 1 1 0 0 0 1 1 0 c 6 1.235 1 1 0 0 0 1 1 1 c 7 1.240 1 1 0 0 1 0 0 0 c 8 1.245 1 1 0 0 1 0 0 1 c 9 1.250 1 1 0 0 1 0 1 0 c a 1.255 1 1 0 0 1 0 1 1 c b 1.260 1 1 0 0 1 1 0 0 c c 1.265 1 1 0 0 1 1 0 1 c d 1.270 1 1 0 0 1 1 1 0 c e 1.275 1 1 0 0 1 1 1 1 c f 1.280 1 1 0 1 0 0 0 0 d 0 1.285 1 1 0 1 0 0 0 1 d 1 1.290 1 1 0 1 0 0 1 0 d 2 1.295 1 1 0 1 0 0 1 1 d 3 1.300 1 1 0 1 0 1 0 0 d 4 1.305 1 1 0 1 0 1 0 1 d 5 1.310
RT8167A 14 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 h1 h0 dac voltage 1 1 0 1 0 1 1 0 d 6 1.315 1 1 0 1 0 1 1 1 d 7 1.320 1 1 0 1 1 0 0 0 d 8 1.325 1 1 0 1 1 0 0 1 d 9 1.330 1 1 0 1 1 0 1 0 d a 1.335 1 1 0 1 1 0 1 1 d b 1.340 1 1 0 1 1 1 0 0 d c 1.345 1 1 0 1 1 1 0 1 d d 1.350 1 1 0 1 1 1 1 0 d e 1.355 1 1 0 1 1 1 1 1 d f 1.360 1 1 1 0 0 0 0 0 e 0 1.365 1 1 1 0 0 0 0 1 e 1 1.370 1 1 1 0 0 0 1 0 e 2 1.375 1 1 1 0 0 0 1 1 e 3 1.380 1 1 1 0 0 1 0 0 e 4 1.385 1 1 1 0 0 1 0 1 e 5 1.390 1 1 1 0 0 1 1 0 e 6 1.395 1 1 1 0 0 1 1 1 e 7 1.400 1 1 1 0 1 0 0 0 e 8 1.405 1 1 1 0 1 0 0 1 e 9 1.410 1 1 1 0 1 0 1 0 e a 1.415 1 1 1 0 1 0 1 1 e b 1.420 1 1 1 0 1 1 0 0 e c 1.425 1 1 1 0 1 1 0 1 e d 1.430 1 1 1 0 1 1 1 0 e e 1.435 1 1 1 0 1 1 1 1 e f 1.440 1 1 1 1 0 0 0 0 f 0 1.445 1 1 1 1 0 0 0 1 f 1 1.450 1 1 1 1 0 0 1 0 f 2 1.455 1 1 1 1 0 0 1 1 f 3 1.460 1 1 1 1 0 1 0 0 f 4 1.465 1 1 1 1 0 1 0 1 f 5 1.470 1 1 1 1 0 1 1 0 f 6 1.475 1 1 1 1 0 1 1 1 f 7 1.480 1 1 1 1 1 0 0 0 f 8 1.485
RT8167A 15 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 h1 h0 dac voltage 1 1 1 1 1 0 0 1 f 9 1.490 1 1 1 1 1 0 1 0 f a 1.495 1 1 1 1 1 0 1 1 f b 1.500 1 1 1 1 1 1 0 0 f c 1.505 1 1 1 1 1 1 0 1 f d 1.510 1 1 1 1 1 1 1 0 f e 1.515 1 1 1 1 1 1 1 1 f f 1.520
RT8167A 16 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. recommended operating conditions (note 4) z supply voltage of controller, v cc -------------------------------------------------------------------- 4.5v to 5.5v z supply voltage of gate driver, v pvcc ---------------------------------------------------------------- 4.5v to 5.5v z battery input voltage, v in ------------------------------------------------------------------------------ 5v to 25v z junction temperature range --------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z vcc to gnd ----------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z pvcc to gnd --------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z rgndx to gnd ------------------------------------------------------------------------------------------- ? 0.3v to 0.3v z tonsetx to gnd ---------------------------------------------------------------------------------------- ? 0.3v to 28v z others ------------------------------------------------------------------------------------------------------- ? 0.3v to (vcc + 0.3v) z bootx to phasex -------------------------------------------------------------------------------------- ? 0.3v to 6.5v z phasex to gnd dc ------------------------------------------------------------------------------------------------------------ ? 0.3v to 28v <20ns ------------------------------------------------------------------------------------------------------- ? 8v to 32v z ugatex to phasex dc ------------------------------------------------------------------------------------------------------------ ? 0.3v to (bootx ? phasex) <20ns ------------------------------------------------------------------------------------------------------- ? 5v to 7.5v z lgatex to gnd dc ------------------------------------------------------------------------------------------------------------ ? 0.3v to (pvcc ? 0.3v) <20ns ------------------------------------------------------------------------------------------------------- ? 2.5v to 7.5v z power dissipation, p d @ t a = 25 c wqfn ? 48l 6x6 ------------------------------------------------------------------------------------------- 2.857w z package thermal resistance (note 2) wqfn ? 48l 6x6, ja ------------------------------------------------------------------------------------- 35 c/w wqfn ? 48l 6x6, jc ------------------------------------------------------------------------------------- 6 c/w z junction temperature ------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------- 200v electrical characteristics parameter symbol test conditions min typ max unit supply input v cc /v pvcc v en = 1.05v, not switching 4.5 5 5.5 v input voltage range v in battery input voltage 5 -- 25 v supply current (v cc + pvcc) i vcc + i pvcc v en = 1.05v, not switching -- 12 20 ma supply current (tonsetx) i tonsetx v fb =1v, v in = 12v, r ton = 100k -- 110 -- a (v cc = 5v, t a = 25 c, unless otherwise specified)
RT8167A 17 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit shutdown current (pvcc + v cc ) i vcc_shdn + i pvcc_shdn v en = 0v -- -- 5 a shutdown current (tonsetx) i tonsetx_shdn v en = 0v -- -- 5 a ton setting tonsetx voltage v tons etx i rton = 80 a, v fbx = 1v 0.95 1.075 1.2 0v on-time t on i rton = 80 a, v fbx = 1v 315 350 385 ns tonsetx input current range i rton v fbx = 1.1v 25 -- 280 a minimum off-time t off_min -- 350 -- ns droop enable / disable drpenx internal current source i drpenx en goes high within 10 s -- 80 -- a droop enable threshold v drpenx detect v drpenx , en goes high within 10 s 4.5 -- -- droop disable threshold v drpenx detect v drpenx , en goes high within 10 s -- -- 2 v gfx vr forced dem gfxps2x enable threshold v gfxps 4.3 -- -- v gfxps2x disable threshold v gfxps -- -- 0.7 v references and system output voltage vid svid setting = 1.000v~1.520v ofs svid setting = 0v ? 0.5 0 0.5 %vid vid svid setting = 0.800v~1.000v ofs svid setting = 0v ? 5 0 5 vid svid setting = 0.500v~0.800v ofs svid setting = 0v ? 8 0 8 vid svid setting = 0.250v~0.500v ofs svid setting = 0v ? 8 0 8 dac accuracy (ps0/ps1) v fbx vid svid setting = 1.100v ofs svid setting = ? 0.640v~0.635v ? 10 0 10 mv v ini_core = 0v, v ini_gfx = 0v 0 0.3125 0.5125 v ini_core = 0.9v, v ini_gfx = 0.9v 0.7375 0.9375 1.1375 v ini_core = 1v, v ini_gfx = 1v 1.3625 1.5625 1.7625 setinix voltage v setinix v ini_core = 1.1v, v ini_gfx = 1.1v 2.6125 -- 5 v offset = 100mv 68 72 -- offset = 50mv 52 56 60 offset = ? 50mv 36 40 44 offset = ? 100mv 20 24 28 external ofsx voltage v ofsx no offset voltage 0 8 12 %v cc impedance of ofsx pin r ofsx 1 -- -- m
RT8167A 18 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit ibias pin voltage v ibias r ibias = 53.6k 2.09 2.14 2.19 v setvid slow 2.5 3.125 3.75 dynamic vid slew rate sr dvid setvid fast 10 12.5 15 mv/ s error amplifier dc gain a dc r l = 47k (note5) 70 80 -- db gain-bandwidth product gbw c load = 5pf (note5) -- 10 -- mhz slew rate sr comp c load = 10pf (gain = ? 4, r load_comp = 47k , v compx = 0.5v to 3v) -- 5 -- v/ s output voltage range v comp r l = 47k 0.5 -- 3.6 v max source/sink current i comp v comp = 2v -- 250 -- a impedance of fbx r fbx 1 -- -- m current sense amplifier input offset voltage v ofs_csa ? 1 -- 1 mv impedance of neg. input r isenxn 1 -- -- m impedance of pos. input r isenxp 1 -- -- m current sense differential input range v csdix v fbx = 1.1v, v csdix = v isenxp ? v isenxn ? 50 -- 100 mv current sense dc gain (loop) a i v fbx = 1.1v, ? 30mv < v csdix < 50mv -- 10 -- v/v v isen linearity v isen_acc v dac = 1.1v ? 30mv < v isen_in < 50mv ? 1 -- 1 % digital current monitor current monitor output voltage (droop enabled) v imonx_enll v fbx = 1v, v isenxn = 0.9v, v rimonfbx = 10k, r imonx = 160k -- 1.6 -- v current monitor output voltage (droop disabled) v imonx_disll v csdix = v isenxp ? v isenxn = 100mv v fbx = 1v, v rimonfbx = 10k, r imonx = 80k -- 1.6 -- v imon voltage range v imon 0 -- 3.3 v digital imon lsb 3.3v / 255 = 12.94mv -- 12.94 -- mv v imonx = 388.3mv, diout [7 : 0] = 30 27 30 33 decimal v imonx = 776.5mv, diout [7 : 0] = 60 57 60 63 decimal digital code of imon c dimon v imonx = 1164.7mv, diout [7 : 0] = 90 87 90 93 decimal update period of digital current monitor t imon -- 1600 -- s gate driver upper driver source r ugatex_sr v bootx ? v phasex = 5v v bootx ? v ugatex = 0.1v -- 1 -- upper driver sink r ugatex_sk v ugatex = 0.1v -- 1 -- lower driver source r lgatex_sr pvcc = 5v, pvcc ? v lgatex = 0.1v -- 1 -- lower driver sink r lgatex_sk v lgatex = 0.1v -- 0.5 -- internal boot charging switch on-resistance r bootx pvcc to bootx -- 30 --
RT8167A 19 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit zero current detection threshold v zc d_th v zcd_th = gnd ? v phasex -- 10 -- mv protection under voltage lock-out threshold v uvlo vcc falling edge 4.04 4.24 -- v under voltage lock-out hysteresis v uvlo -- 100 -- mv over voltage protection threshold v ovp respect to vout_max svid , with 1 s filter time 100 150 200 mv under voltage protection threshold v uvp v uvp = v isenxn ? v refx , 0.8v < v refx <1.52v, with 3 s filter time ? 350 ? 300 ? 250 mv negative voltage protection threshold v nvp v nvp = v isenxn ? gnd ? 100 ? 50 -- mv current sense gain for over current protection a oc v ocset = 2.4v v isenxp ? v isenxn = 50mv -- 48 -- v/v logic inputs logic-high v ih with respect to 1v, 70% 0.7 -- -- v en input threshold voltage logic-low v il with respect to 1v, 30% -- -- 0.3 v leakage current of en ? 1 -- 1 a v ih with respect to intel spec. 0.65 -- -- v vclk,vdio input threshold voltage v il with respect to intel spec. -- -- 0.45 v leakage current of vclk, vdio i leak_in ? 1 -- 1 a alert alert low voltage v alert i alert_ sink = 4ma -- -- 0.4 v vr ready vrx_ready low voltage v vr x_ready i vrx_ready_ sink = 4ma -- -- 0.4 v vrx_ready delay t vrx_ready v isenxn = v boot to v vrx_ready high 70 100 160 s thermal throttling vrhot output voltage v vrhot i vrhot_sink = 40ma -- 0.4 -- v high impedance output alert, vrx_ready, vrhot i leak_out ? 1 -- 1 a temperature zone tsen threshold for tmp_zone [7] transition 100c -- 1.8725 -- v tsen threshold for tmp_zone [6] transition 97c -- 1.8175 -- v tsen threshold for tmp_zone [5] transition 94c -- 1.7625 -- v tsen threshold for tmp_zone [4] transition 91c -- 1.7075 -- v tsen threshold for tmp_zone [3] transition v tsenx 88c -- 1.6525 -- v
RT8167A 20 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guaranteed by design. parameter symbol test conditions min typ max unit tsen threshold for tmp_zone [2] transition 85c -- 1.5975 -- v tsen threshold for tmp_zone [1] transition 82c -- 1.5425 -- v tsen threshold for tmp_zone [0] transition v tsenx 75c -- 1.4875 -- v update period t tsen -- 1600 -- s adc latency t lat -- -- 400 s c iccmax1 v iccmax = 0.637v 29 32 35 decimal c iccmax2 v iccmax = 1.2642v 61 64 67 decimal digital code of iccmax c iccmax3 v iccmax = 2.5186v 125 128 131 decimal c iccmaxa1 v iccmaxa = 0.1666v 5 8 11 decimal c iccmaxa2 v iccmaxa = 0.3234v 13 16 19 decimal digital code of iccmaxa c iccmaxa3 v iccmaxa = 0.637v 29 32 35 decimal c tmpmax1 v tmpmax = 1.6758v 82 85 88 decimal c tmpmax2 v tmpmax = 1.9698v 97 100 103 decimal digital code of tmpmax c tmpmax3 v tmpmax = 2.4598v 122 125 128 decimal
RT8167A 21 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics boot vid = 1v time (100 s/div) core vr power on from en en (2v/div) v core (500mv/div) vr_ready (2v/div) ugate (20v/div) time (100 s/div) core vr power off from en boot vid = 1v en (2v/div) v core (500mv/div) vr_ready (2v/div) ugate (20v/div) vid = 1.1v time (100 s/div) core vr ocp i load (10a/div) v core (1v/div) vr_ready (1v/div) ugate (20v/div) time (40 s/div) core vr ovp and nvp vid = 1.1v lgate (10v/div) v core (1v/div) vr_ready (1v/div) ugate (20v/div) 0.7v to 1.2v, slew rate = slow, i load = 4a time (40 s/div) core vr dynamic vid up vdio (2v/div) vclk (2v/div) v core (500mv/div) alert (2v/div) time (40 s/div) core vr dynamic vid down 1.2v to 0.7v, slew rate = slow, i load = 4a alert (2v/div) v core (500mv/div) vdio (2v/div) vclk (2v/div)
RT8167A 22 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (10 s/div) core vr dynamic vid up 0.7v to 1.2v, slew rate = fast, i load = 4a vdio (2v/div) vclk (2v/div) v core (500mv/div) alert (2v/div) time (10 s/div) core vr dynamic vid down 1.2v to 0.7v, slew rate = fast, i load = 4a v core (500mv/div) alert (2v/div) vdio (2v/div) vclk (2v/div) vid = 1.1v, i load = 1a to 8a, slew time = 150ns time (100 s/div) core vr load transient v core (20mv/div) 8 1 i load (a/div) time (100 s/div) core vr load transient vid = 1.1v, i load = 8a to 1a, slew time = 150ns v core (20mv/div) 8 1 i load (a/div) vid = 1.1v, ps0 to ps2, i load = 0.2a time (100 s/div) core vr mode transition ugate (20v/div) vclk (1v/div) lgate (10v/div) v core (20mv/div) time (100 s/div) core vr mode transition vid = 1.1v, ps2 to ps0, i load = 0.2a ugate (20v/div) v core (20mv/div) vclk (1v/div) lgate (10v/div)
RT8167A 23 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (100 s/div) gfx vr ocp i load (5a/div) v gfx (1v/div) vra_ready (1v/div) ugatea (20v/div) time (40 s/div) gfx vr ovp and nvp vid = 1.1v lgatea (10v/div) v gfx (1v/div) vra_ready (1v/div) ugatea (20v/div) time (100 s/div) gfx vr power on from en boot vid = 1v en (2v/div) v gfx (500mv/div) vra_ready (2v/div) ugatea (20v/div) time (100 s/div) gfx vr power off from en boot vid = 1v ugatea (20v/div) en (2v/div) v gfx (500mv/div) vra_ready (2v/div) tsen sweep from 1.7v to 1.9v time (10ms/div) core vr thermal monitoring vrhot (500mv/div) tsen (v/div) 1.9 1.7 core vr v ref vs. temperature 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 -50 -25 0 25 50 75 100 125 temperature (c) v ref (v)
RT8167A 24 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (40 s/div) gfx vr dynamic vid 0.7v to 1.2v, slew rate = slow, i load = 1.25a vdio (2v/div) vclk (2v/div) v gfx (500mv/div) alert (2v/div) time (40 s/div) gfx vr dynamic vid alert (2v/div) v gfx (500mv/div) 1.2v to 0.7v, slew rate = slow, i load = 1.25a vdio (2v/div) vclk (2v/div) time (10 s/div) gfx vr dynamic vid 0.7v to 1.2v, slew rate = fast, i load = 1.25a vdio (2v/div) vclk (2v/div) v gfx (500mv/div) alert (2v/div) time (10 s/div) gfx vr dynamic vid alert (2v/div) 1.2v to 0.7v, slew rate = fast, i load = 1.25a vdio (2v/div) vclk (2v/div) v gfx (500mv/div) time (100 s/div) gfx vr load transient vid = 1.1v, i load = 1a to 4a, slew time = 150ns v gfx (20mv/div) 4 1 i load (a/div) time (100 s/div) gfx vr load transient vid = 1.1v, i load = 4a to 1a, slew time = 150ns v gfx (20mv/div) 4 1 i load (a/div)
RT8167A 25 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (100 s/div) gfx vr mode transition vid = 1.1v, ps2 to ps0, i load = 0.1a ugatea (20v/div) v gfx (20mv/div) vclk (1v/div) lgatea (10v/div) time (100 s/div) gfx vr mode transition vid = 1.1v, ps0 to ps2, i load = 0.1a ugatea (20v/div) vclk (1v/div) lgatea (10v/div) v gfx (20mv/div) time (10ms/div) gfx vr thermal monitoring tsena sweep from 1.7v to 1.9v 1.9 1.7 tsena (v/div) vrhot (500mv/div) gfx vr v ref vs. temperature 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 -50-25 0 255075100125 temperature (c) v ref (v)
RT8167A 26 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. management states and vid on-the-fly function. the power management states include dem in ps2/ps3 and forced- ccm in ps1/ps0. the vid on-the-fly function has three different slew rates : fast, slow and decay. the RT8167A integrates a high accuracy adc for platform setting functions, such as no-load offset and over current level. the controller supports both dcr and sense-resistor current sensing. the RT8167A provides vr ready output signals of both core vr and gfx vr. it also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and under voltage lockout. the RT8167A is available in a wqfn- 48l 6x6 small foot print package. design tool to help users reduce efforts and errors caused by manual calculations, a user-friendly design tool is now available on request. this design tool calculates all necessary design parameters by entering user's requirements. please contact richtek's representatives for details. serial vid (svid) interface svid is a three-wire serial synchronous interface defined by intel. the three wire bus includes vdio, vclk and alert signals. the master (intel's vr12/imvp7 cpu) initiates and terminates svid transactions and drives the vdio, vclk, and alert during a transaction. the slave (RT8167A) receives the svid transactions and acts accordingly. application information the RT8167A is a vr12/imvp7 compliant, dual single- phase synchronous buck pwm controller for the cpu core vr and gfx vr. the gate drivers are embedded to facilitate pcb design and reduce the total bom cost. a serial vid (svid) interface is built-in in the RT8167A to communicate with intel vr12/imvp7 compliant cpu. the RT8167A adopts g-navp tm (green native avp), which is richtek's proprietary topology derived from finite dc gain compensator, making it an easy setting pwm controller to meet avp requirements. the load line can be easily programmed by setting the dc gain of the error amplifier. the RT8167A has fast transient response due to the g-navp tm commanding variable switching frequency. g-navp tm topology also represents a high efficiency system with green power concept. with g-navp tm topology, the RT8167A becomes a green power controller with high efficiency under heavy load, light load, and very light load conditions. the RT8167A supports mode transition function between ccm and dem. these different operating states allow the overall power system to have low power loss. by utilizing the g-navp tm topology, the operating frequency of RT8167A varies with output voltage, load and vin to further enhance the efficiency even in ccm. the built-in high accuracy dac converts the svid code ranging from 0.25v to 1.52v with 5mv per step. the differential remote output voltage sense and high accuracy dac allow the system to have high output voltage accuracy. the RT8167A supports vr12/imvp7 compatible power
RT8167A 27 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. standard serial vid command code commands master payload contents slave payload contents description 00h not supported n/a n/a n/a 01h setvid_fast vid code n/a set new target vid code, vr jumps to new vid target with controlled default ?fast? slew rate 12.5mv/ s. 02h setvid_slow vid code n/a set new target vid code, vr jumps to new vid target with controlled default ?slow? slew rate 3.125mv/ s. 03h setvid_decay vid code n/a set new target vid code, vr jumps to new vid target, but does not control the slew rate. the output voltage decays at a rate proportional to the load current 04h setps byte indicating power states n/a set power state 05h setregadr pointer of registers in data table n/a set the pointer of the data register 06h setreg dat new data register content n /a w rite the contents to the data regi ster 07h getreg pointer of registers in data table specified register contents slave returns the contents of the specified register as the payload 08h - 1fh not supported n/a n/a n/a
RT8167A 28 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. data and configuration register index register name description access default 00h vendor id vendor id, default 1eh. ro, vendor 1eh 01h product id product id. ro, vendor 65h 02h product revision product revision. ro, vendor 01h 05h protocol id svid protocol id. ro, vendor 01h 06h vr_capability bit mapped register, identifies the svid vr capabilities and which of the optional telemetry register are supported. ro, vendor 81h 10h status_1 data register containing the status of vr. r-m, w-pwm 00h 11h status-2 data register containing the status of transmission. r-m, w-pwm 00h 12h temperature zone data register showing temperature zone that have been entered. r-m, w-pwm 00h 15h output_current data register showing direct adc conversion of averaged output current. r-m, w-pwm 00h 1ch status_2_lastread the register contains a copy of the status_2. r-m, w-pwm 00h 21h icc_max data register containing the maximum icc of platform supports. binary format in amp, ie 64h = 100a. ro, platform -- 22h temp_max data register containing the temperature max the platform supports. binary format in c, ie 64h = 100c only for core vr ro, platform -- 24h sr-fast data register containing the capability of fast slew rate the platform can sustains. binary format in mv/ s, ie 0ah = 10mv/ s. ro 0ah 25h sr-slow data register containing the capability of slow slew rate. binary format in mv/ s ie 02h = 2.5mv/ s. ro 02h 30h vout_max the register is programmed by the master and sets the maximum vid. rw, ma ste r b fh 31h vid setting data register containing currently programmed vid. rw, master 00h 32h power state register containing the current programmed power state. rw, master 00h 33h offset set offset in vid steps. rw, master 00h 34h multi vr config bit mapped data register which configures multiple vrs behavior on the same bus. rw, master 00h 35h pointer scratch pad register for temporary storage of the setregadr pointer register. rw, master 30h notes : ro = read only rw = read/write r-m = read by master w-pwm = write by pwm only vendor = hard coded by vr vendor platform = programmed by platform master = programmed by the master pwm = programmed by the vr control ic
RT8167A 29 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. iccmax, iccmaxa and tmpmax the RT8167A provides iccmax, iccmaxa and tmpmax pins for platform users to set the maximum level of output current or vr temperature: iccmax for core vr maximum current, iccmaxa for gfx vr maximum current, and tmpmax for core vr maximum temperature. to set iccmax, iccmaxa and tmpmax, platform designers should use resistive voltage dividers on these three pins. the current of the divider should be several milli-amps to avoid noise effect. the three items share the same algorithms : the adc divides 5v into 255 levels. therefore, lsb = 5/255 = 19.6mv, which means 19.6mv applied to iccmax pin equals to 1a setting. for example, if a platform designer wants to set tmpmax to 120 c, the voltage applied to tmpmax should be 120 x 19.6mv = 2.352v. the adc circuit inside these three pins will decode the voltage applied and store the maximum current/ temperature setting into icc_max and temp_max registers. the adc monitors and decodes the voltage at these three pins only after en = high. if en = low, the RT8167A will not take any action even when the vr output current or temperature exceeds its maximum setting at these adc pins. the maximum level settings at these adc pins are different from over current protection or over temperature protection. that means, these maximum level setting pins are only for platform users to define their system operating conditions and these messages will only be utilized by the cpu. precise reference current generation the RT8167A includes extensive analog circuits inside the controller. these analog circuits need very precise reference voltage/current to drive these analog devices. the RT8167A will auto-generate a 2.14v voltage source at ibias pin, and a 53.6k resistor is required to be connected between ibias and analog ground. through this connection, the RT8167A generates a 40 a current from ibias pin to analog ground and this 40 a current will be mirrored inside the RT8167A for internal use. other types of connection or other values of resistance applied at the ibias pin may cause failure of the RT8167A's analog circuits. thus a 53.6k resistor is the only recommended component to be connected to the ibias pin. the resistance accuracy of this resistor is recommended to be at least 1%. figure 4. ibias setting + - ibias 53.6k current mirror + - 2.14v power ready detection and power on reset (por) during start-up, the RT8167A detects the voltage on the voltage input pins : vcc and en. when vcc > v uvlo , the RT8167A will recognize the power state of system to be ready (por = high) and wait for enable command at en pin. after por = high and en > v enth , the RT8167A will enter start-up sequence for both core vr and gfx vr. if the voltage on any voltage pin drops below por threshold (por = low), the RT8167A will enter power down sequence and all the functions will be disabled. svid will be invalid within 300 s after chip becomes enabled. all the protection latches (ovp, ocp, uvp, otp) will be cleared only after por = low. en = low will not clear these latches. figure 3. power ready detection and power on reset (por) v u v l o v e n t h + - + - por chip en vcc en
RT8167A 30 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 6. setini and setinia pin voltage setting start up sequence the RT8167A utilizes internal soft-start sequence which strictly follows intel vr12/imvp7 start up sequence specifications. after por = high and en = high, a 300 s delay is needed for the controller to determine whether all the power inputs are ready for entering start up sequence. if pin voltage of setini/setinia is zero, the output voltage of core/gfx vr is programmed to stay at 0v. if pin voltage of setini/setinia is not zero, vr output voltage will ramp up to initial boot voltage (v ini_core , v ini_gfx ) after both por = high and en = high. after the output voltage of core/gfx vr reaches target initial boot voltage, the controller will keep the output voltage at the initial boot voltage and wait for the next svid commands. after the RT8167A receives valid vid code (typically setvid_slow command), the output voltage will ramp up/down to the target voltage with specified slew rate. after the output voltage reaches the target voltage, the RT8167A will send out vr_ready signal to indicate the power state of the RT8167A is ready. the vr_ready circuit is an open- drain structure so a pull-up resistor is recommended for connecting to a voltage source. power down sequence similar to the start up sequence, the RT8167A also utilizes a soft shutdown mechanism during turn-off. after por = low, the internal reference voltage (positive terminal of compensation ea) starts ramping down with 3.125mv/ s slew rate, and output voltage will follow the reference voltage to 0v. after output voltage drops below 0.2v, the RT8167A shuts down and all functions are disabled. the vr_ready will be pulled down immediately after por = low. v ini_core and v ini_gfx setting the initial start up voltage (v ini_core , v ini_gfx ) of the RT8167A can be set by platform users through setini and setinia pins. voltage divider circuit is recommended to be applied to setini and setinia pins. the v ini_core / v ini_gfx relate to setini/setinia pin voltage setting as shown in figure 6. recommended voltage setting at setini and setinia pins are also shown in figure 6. figure 5. adc pins setting a/d converter iccmax iccmaxa tmpmax v cc v ini_core v ini_gfx recommended setini/setinia pin voltage 1.1v 5 8 x vcc P 3.125v or vcc 1v 3 8 x vcc P 1.875v 0.9v 3 16 x vcc P 0.9375v 0v 1 16 x vcc P 0.3125v or gnd v c c ( 5 v ) g n d 1 / 8 v c c 1 / 4 v c c 1 / 2 v c c v i n i _ c o r e = 0 . 9 v v i n i _ g f x = 0 . 9 v v i n i _ c o r e = 1 . 1 v v i n i _ g f x = 1 . 1 v v i n i _ c o r e = 1 v v i n i _ g f x = 1 v v i n i _ c o r e = 0 v v i n i _ g f x = 0 v
RT8167A 31 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 7 (a). power sequence for RT8167A (v ini_core = v ini_gfx = 0v) figure 7 (b). power sequence for RT8167A (v ini_core 0, v ini_gfx 0v) en svid valid xx xx v core vr_ready 100s por 0.2v core vr operation mode ccm ccm 0.2v v gfx svid defined ccm svid defined gfx vr operation mode 100s vra_ready ccm 300s off off vcc en chip (internal signal) off off vra_ready en chip (internal signal) svid valid xx xx v core vr_ready 100s por 0.2v core vr operation mode ccm ccm off 0.2v v gfx svid defined ccm off svid defined gfx vr operation mode ccm 250s off off vcc en 100s 300s v ini_gfx v ini_core 50s
RT8167A 32 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 8. simplified schematic for droop and remote sense in ccm disable gfx vr : before en = high gfx vr enable or disable is determined by the internal circuitry that monitors the isenan voltage during start up. before en = high, gfx vr detects whether the voltage of isenan is higher than ? vcc ? 1v ? to disable gfx vr. the unused driver pins can be connected to gnd or left floating. gfx vr forced-dem function enable : after vra_ready = high the gfx vr's forced-dem function can be enabled or disabled with gfxps2 pin. the RT8167A detects the voltage of gfxps2 for forced-dem function. if the voltage at gfxps2 pin is higher than 4.3v, the gfx vr operates in forced-dem. if this voltage is lower than 0.7v, the gfx vr follows svid power state command. loop control both core and gfx vr adopt richtek's proprietary g- navp tm topology. g-navp tm is based on the finite-gain valley current mode with ccrcot (constant current ripple constant on time) topology. the output voltage, v core or v gfx , will decrease with increasing output load current. the control loop consists of pwm modulator with power stage, current sense amplifier and error amplifier as shown in figure 8. similar to the valley current mode control with finite compensator gain, the high side mosfet on-time is determined by the ccrcot pwm generator. when load current increases, v cs increases, the steady state comp voltage also increases which makes the output voltage decrease, thus achieving avp. droop function enable the core/gfx vr's droop function can be enabled or disabled with drpen/drpena pin. after en = high within 10 s, the RT8167A will source 80 a current from drpen/ drpena pin to the external resistor to determine the voltage level. if the voltage at drpen/drpena pin is lower than 3.5v, then the vr will operate in droop-disabled mode. if the voltage is higher than 4v, then the vr will operate in droop-enabled mode. droop setting (with temperature compensation) it's very easy to achieve the active voltage positioning (avp) by properly setting the error amplifier gain due to the native droop characteristics. the target is to have v out = v refx ? i load x r droop (1) then solving the switching condition v compx = v csx in figure 8 yields the desired error amplifier gain as where a i is the internal current sense amplifier gain and r sense is the current sense resistance. if no external sense resistor is present, the dcr of the inductor will act as r sense . r droop is the resistive slope value of the converter output and is the desired static output impedance. figure 9. error amplifier gain (a v ) influence on v out accuracy a v1 a v2 a v2 > a v1 v out load current 0 == i sense v droop ar r2 a r1 r (2) v in isenxp isenxn fbx rgndx high side mosfet l r x c x r c c r1 r2 core/gfx vr v cc_sense compx v csx c2 c1 vrefx gfx/core vr ccrcot pwm generator driver logic control c byp ugatex phasex lgatex core/gfx vr v ss_sense v out (v core /v gfx ) + - + - ea + - ai + - cmp low side mosfet
RT8167A 33 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. loop compensation optimized compensation of the core vr allows for best possible load step response of the regulator's output. a type-i compensator with one pole and one zero is adequate for a proper compensation. figure 10 shows the compensation circuit. it was previously mentioned that to determine the resistive feedback components of error amplifier gain, c1 and c2 must be calculated for the compensation. the target is to achieve constant resistive output impedance over the widest possible frequency range. the pole frequency of the compensator must be set to compensate the output capacitor esr zero : where c is the capacitance of the output capacitor and r c is the esr of the output capacitor. c2 can be calculated as follows : the zero of compensator has to be placed at half of the switching frequency to filter the switching-related noise. such that, ton setting high frequency operation optimizes the application by trading off efficiency due to higher switching losses with smaller component size. this may be acceptable in ultra- portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low frequency operation offers the best overall efficiency at sense, hot ntc, hot ntc, cold sense, cold sense, hot sense, cold r1b r (r1a // r ) (r1a // r ) r r 1 r = ? ?? ? ?? ?? (8) p c 1 f 2cr = (9) c cr c2 r2 = (10) (11) () ntc, 25 c sw 1 c1 r1b r1a // r f = + since the dcr of inductor is temperature dependent, it affects the output accuracy in high temperature conditions. temperature compensation is recommended for the lossless inductor dcr current sense method . figure 10 shows a simple but effective way of compensating the temperature variations of the sense resistor using an ntc thermistor placed in the feedback path. figure 10. loop setting with temperature compensation usually, r1a is set to equal r ntc (25 c), while r1b is selected to linearize the ntc's temperature characteristic. for a given ntc, the design would be to obtain r1b and r2 and then c1 and c2. according to (2), to compensate the temperature variations of the sense resistor, the error amplifier gain (a v ) should have the same temperature coefficient with r sense . hence from (2), we can have av at any temperature (t) as the standard formula for the resistance of ntc thermistor as a function of temperature is given by : where r ntc, 25 is the thermistor's nominal resistance at room temperature, (beta) is the thermistor's material constant in kelvins, and t is the thermistor's actual temperature in celsius. the dcr value at different temperatures can be calculated using the equation below : dcr t = dcr 25 x [1+0.00393 x (t-25)] (6) where 0.00393 is the temperature coefficient of copper. for a given ntc thermistor, solving (4) at room temperature (25 c) yields v, hot sense, hot v, cold sense, cold ar ar = (3) v, t ntc, t r2 a r1a / /r r1b = + (4) ( ) ( ) { } 11 t+273 298 ntc, t ntc, 25 rr e ?? ? ?? ?? = (5) v cc_sense - + v ss_sense fbx rgndx compx c2 c1 r2 r1b ea r1a ntc - + vrefx r2 = a v, 2 5 x (r1b + r1a // r ntc, 25 ) (7) where a v, 2 5 c is the error amplifier gain at room temperature obtained from (2). r1b can be obtained by substituting (7) to (3),
RT8167A 34 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 11. on-time setting with rc filter (12) <= ? -12 tonsetx onx refx in refx 28 10 r t (v 1.2v) vv (13) = ? onx refx -12 tonsetx refx in refx t (v 1.2v) 23.33 10 r v vv (14) ? ? ?? = ? ?? + +? ?? ?? + ? ?? s(max) on hs delay refx(max) load(max) on _ ls fet droop in(max) load(max) on _ ls fet on _ hs fet 1 f(khz) tt vi r dcrr vi r r the expense of component size and board space. figure 11 shows the on-time setting circuit. connect a resistor (r tonsetx ) between v in and tonsetx to set the on-time of ugatex : where t onx is the ugatex turn on period, vin is the input voltage of converter, and v refx is the internal reference voltage. when v refx is larger than 1.2v, the equivalent switching frequency may be over the maximum design range, making it unacceptable. therefore, the vr implements a pseudo- constant-frequency technology to avoid this disadvantage of ccrcot topology. when v refx is larger than 1.2v, the on-time equation will be modified to : on-time translates roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in external high side mosfet. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only in ccm during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, phasex goes high earlier than normal, extending the on-time by a period equal to the high side mosfet rising dead time. for better efficiency of the given load range, the maximum switching frequency is suggested to be : where f s(max) is the maximum switching frequency, t hs- delay is the turn on delay of high side mosfet, v refx(max) is the maximum application dac voltage of application, v in(max) is the maximum application input voltage, i load(max) is the maximum load of application, r on_ls-fet is the low side mosfet r ds(on) , r on_hs-fet is the high side mosfet r ds(on) , dcr l is the inductor dcr, and r droop is the load line setting. gfx/core vr ccrcot pwm generator tonsetx r tonsetx r1 c1 v in vrefx on-time differential remote sense setting the core/gfx vr includes differential, remote-sense inputs to eliminate the effects of voltage drops along the pc board traces, cpu internal power routes and socket contacts. the cpu contains on-die sense pins core/ gfx v cc_sense and v ss_sense . connect rgndx to core/ gfx v ss_sense . connect fbx to core/gfx v cc_sense with a resistor to build the negative input path of the error amplifier. the precision voltage reference v refx is referred to rgnd for accurate remote sensing. current sense setting the current sense topology of the core/gfx vr is continuous inductor current sensing. therefore, the controller can be less noise sensitive. low offset amplifiers are used for loop control and over current detection. the internal current sense amplifier gain (a i ) is fixed to be 10. the isenxp and isenxn denote the positive and negative input of the current sense amplifier. users can either use a current sense resistor or the inductor's dcr for current sensing. using inductor's dcr allows higher efficiency as shown in figure 12. to let then the transient performance will be optimum. for example, choose l = 0.36 h with 1m dcr and c x = 100nf, to yields for r x : x x l rc dcr = (15) x 0.36 h r3.6k 1m 1 0 0 n f == ? (16) l dcr r x c x v out (v core /v gfx ) c byp + - isenxp isenxn phasex a i v csx figure 12. lossless inductor sensing
RT8167A 35 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. considering the inductance tolerance, the resistor r x has to be tuned on board by examining the transient voltage. if the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, r x is too small. vice versa, if the resistance is too large the output voltage transient will only have a small initial dip and the recovery will be too fast, causing a ring-back. using current-sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. considering the equivalent inductance (l esl ) of the current sense resistor, a rc filter is recommended. the rc filter calculation method is similar to the above-mentioned inductor dcr sensing method. no-load offset the RT8167A provides a no-load offset function which has four-level offsets of output voltage for the core/gfx vr. the no-load offset function is implemented through the ofsx pin. a voltage divider circuit is recommended to be applied to ofsx pins. the output offset voltage relation to the ofsx pin voltage setting is shown in figure 13. recommended voltage setting at ofs and ofsa pins are also shown in figure 13. v c c ( 5 v ) g n d 0 . 1 6 v c c 0 . 3 2 v c c 0 . 4 8 v c c 0 . 6 4 v c c o f f s e t v o l t a g e = 1 0 0 m v o f f s e t v o l t a g e = 5 0 m v o f f s e t v o l t a g e = - 5 0 m v o f f s e t v o l t a g e = - 1 0 0 m v o f f s e t v o l t a g e = 0 m v offset voltage recommended ofs/ofsa pin voltage 100mv 0.8 x vcc P 4v or vcc 50mv 0.56 x vcc P 2.8v ? 50mv 0.4 x vcc P 2v ? 100mv 0.24 x vcc P 1.2v 0mv gnd figure 13. ofs and ofsa pins voltage setting operation mode transition the RT8167A supports operation mode transition function in core/gfx vr for the setps command of intel's vr12/ imvp7 cpu. the default operation mode of the RT8167A's core/gfx vr is ps0, which is ccm operation. the other operation mode is ps2 (dem operation). figure 14. thermal monitoring circuit to meet intel's vr12/imvp7 specification, platform users have to set the tsen voltage to meet the temperature variation of vr from 75% to 100% vr max temperature. for example, if the vr max te mperature is 100 c, platform users have to set the tsen voltage to be 1.4875v when vr temperature reaches 75 c and 1.8725v when vr temperature reaches 100 c. detailed voltage setting versus temperature variation is shown in table 2. thermometer code is implemented in the temperature zone register. tsenx v cc r 1 r 2 r 3 r ntc after receiving setps command, the core/gfx vr will immediately change to the new operation state. when vr receives setps command of ps2 operation mode, the vr operates as a dem controller. if vr receives dynamic vid change command (setvid), vr will automatically enter ps0 operation mode. after output voltage reaches target voltage, vr will stay at ps0 state and ignore former setps command. only by re-sending setps command after setvid command will vr be forced into ps2 operation state again. thermal monitoring and temperature reporting core/gfx vr provides thermal monitoring function via sensing tsen pin voltage. through the voltage divider resistors r1, r2, r3 and r ntc , the voltage of tsen will be proportional to vr temperature. when vr temperature rises, the tsenx voltage also rises. the adc circuit of vr monitors the voltage variation at tsenx pin from 1.47v to 1.89v with 55mv resolution, and this voltage is decoded into digital format and stored into the temperature zone register.
RT8167A 36 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 2. temperature zone register vrhot svid thermal alert comparator trip points temperatures scaled to maximum = 100% voltage represents assert bit minimum level b7 b6 b5 b4 b3 b2 b1 b0 100% 97% 94% 91% 88% 85% 82% 75% 1.855v 1.8v 1.745 v 1.69 v 1.635 v 1.58 v 1.52 5v 1.47 v tsen pin voltage temperature_zone register content 1.855 v tsen 1111 _ 1111 1.800 v tsen 1.835 0111_1111 1.745 v tsen 1.780 0011_1111 1.690 v tsen 1.725 0001_1111 1.635 v tsen 1.670 0000_1111 1.580 v tsen 1.615 0000_0111 1.525 v tsen 1.560 0000_0011 1.470 v tsen 1.505 0000_0001 v tsen < 1.470 0000_0000 current monitoring and current reporting the core/gfx vr provides current monitoring function via sensing the voltage difference of imonfbx pin and output voltage. figure 15 shows the current monitoring setting principle. the equivalent output current will be sensed from imonfbx pin and mirrored to imonx pin. the resistor connected to imonx pin determines voltage gain of the imon output. the RT8167A supports two temperature reporting, vrhot(hardware reporting) and alert(software reporting), to fulfill vr12/imvp7 specification. vrhot is an open-drain structure which sends out active-low vrhot signals. when tsen voltage rises above 1.855v (100% of vr temperature), the vrhot signal will be set to low. when tsen voltage drops below 1.8v (97% of vr temperature), the vrhot signal will be reset to high. when tsen voltage rises above 1.8v (97% of vr temperature), the RT8167A will update the bit1 data from 0 to 1 in the status_1 register and assert alert. when tsen voltage drops below 1.745v (94% of vr temperature), vr will update the bit1 data from 1 to 0 in the status_1 register and assert alert. the temperature reporting function for the gfx vr can be disabled by pulling tsena pin to vcc in case the temperature reporting function for the gfx vr is not used or the gfx vr is disabled. when the gfx vr's temperature reporting function is disabled, the RT8167A will reject the svid command of getting the temperature_zone register content of the gfx vr. however, note that the temperature reporting function for the core vr is always active. core vr's temperature reporting function can not be disabled by pulling tsen pin to vcc. figure 15. current monitor setting principle r imonfb v cc_sense imonfbx c1 v imon r imon current monitor imonx - + vrefx vrefx + 2 (v isenxp - v isenxn ) 0ll en i mirror the voltage of imonfbx is different when vr operates in droop enable mode and droop disable mode : droop enable mode : v imonfbx = v refx (17) droop disable mode : v imonfbx = v refx + 2 (v isenxp ? v isenxn ) (18) the current monitor indicator v imon equation is shown as: imonfbx cc _ sense imon imon imonfb (i v ) r v r ? = (19) where v imonfbx is the pin voltage of imonfbx, v cc_sense is the output voltage of core/gfx vr, and r imon and r imonfb are the current monitor current setting resistors. the maximum voltage of current monitoring will be limited at 3.3v. platform designers have to design the r imon to meet the maximum voltage of imon at full load. when vr operates in droop enable mode, find r imon and r imonfb based on : imon(max) imon imonfb (max) droop v r rir = (20) where v imon(max) is the maximum voltage at full load, r droop is the load line setting of vr, and i max is the full load current of vr.
RT8167A 37 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 17. ocp setting with temperature compensation ocsetx v cc r oc1b r oc2 r oc1a ntc usually, r oc1a is selected to be equal to the thermistor's nominal resistance at room temperature. ideally, v ocset is assumed to have the same temperature coefficient as r sense (inductor dcr) : according to the basic circuit calculation, v ocset can be obtained at any temperature : ocset, hot sense, hot ocset, cold sense, cold vr vr = (24) oc2 ocset, t cc oc1a ntc, t oc1b oc2 r vv r//r r r = ++ (25) re-write (24) from (25), to get v ocset at room temperature oc1a ntc, cold oc1b oc2 sense, hot oc1a ntc, hot oc1b oc2 sense, cold r//r r r r r//r r r r ++ = ++ (26) (27) ocset, 25 oc2 cc oc1a ntc, 25 oc1b oc2 v r v r//r r r = ++ (23) cc oc1 oc2 ocset v rr 1 v ?? = ? ?? ?? figure 16. ocp setting without temperature compensation v cc ocsetx r oc1 r oc2 the current limit is triggered when inductor current exceeds the current limit threshold i limit , defined by v ocset . the driver will be forced to turn off ugate until the over current condition is cleared. if the over current condition remains valid for 15 pwm cycles, vr will trigger ocp latch. latched ocp forces both ugate and lgate to go low. when ocp is triggered in one of vrs, the other vr will enter into soft shutdown sequence. the ocp latch mechanism will be masked when vrx_ready = low, which means that only the current limit will be active when v out is ramping up to initial voltage (or v refx ). if inductor dcr is used as the current sense component, then temperature compensation is recommended for protection under all conditions. figure 17 shows a typical ocp setting with temperature compensation. when vr operate in droop disable mode, r imon and r imonfb can be obtained according to equation below : imon(max) imon imonfb (max) sense v r rir2 = (21) where v imon(max) is the maximum voltage at full load, r sense is the equivalent resistance of current sense circuit, and i max is the full load current of vr. the adc circuit of the core/gfx vr monitors the voltage variation at the imon pin from 0v to 3.3v, and this voltage is decoded into digital format and stored into the output_current register. the adc divides 3.3v into 255 levels, so lsb = 3.3v/255 = 12.941mv. platform designers should design v imonx to be 3.3v at iccmax. for example, when load current = 0.5 x iccmax, v imon = 1.65v and output_current register = 7fh. the imon pin is the output of internal operational amplifier and sends out imon signal. when imon voltage rises above 3.3v (100% of vr output current), the vr will update the bit2 data from 0 to 1 in the status_1 register. the 1 in bit2 of status_1 register will be cleared to 0 only after the master (usually intel's vr12/imvp7 cpu) executes getreg command to status_1 register. over current protection the core/gfx vr compares a programmable current limit set point to the voltage from the current sense amplifier output for over current protection (ocp). the voltage applied to ocsetx pin defines the desired peak current limit threshold i limit : v ocset = 48 x i limit x r sense (22) connect a resistive voltage divider from vcc to gnd, with the joint of the resistive divider connected to ocset pin as shown in figure 16. for a given r oc2 , then
RT8167A 38 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. solving (26) and (27) yields r oc1b and r oc2 (28) oc2 equ, hot equ, cold equ, 25 cc ocset, 25 r rr (1)r v (1 ) v = ? + ? ? (29) oc1b equ, hot equ, cold r (1)r2 r r (1 ) = ? + ? ? where sense, hot 25 hot sense, cold 25 cold r dcr [1 0.00393 (t 25)] r dcr [1 0.00393 (t 25)] = + ? = + ? (30) r equ, t = r oc1a // r ntc, t (31) over voltage protection (ovp) the over voltage protection circuit of core/gfx vr monitors the output voltage via the isenxn pin. the supported maximum operating vid of vr (v (max) ) is stored in the v out(max) register. once v isenxn exceeds ? v (max) + 200mv ? , ovp is triggered and latched. vr will try to turn on low side mosfets and turn off high side mosfets to protect cpu. when ovp is triggered by the one of the vrs, the other vr will enter soft shutdown sequence. a 10 s delay is used in ovp detection circuit to prevent false trigger. negative voltage protection (nvp) during ovp latch state, both core/gfx vrs also monitor isenxn pin for negative voltage protection. since the ovp latch will continuously turn on low side mosfet of vr, vr may suffer negative output voltage. therefore, when the voltage of isenxn drops below ? 0.05v after triggering ovp, vr will turn off low side mosfets while high side mosfets remain off. the nvp function will be active only after ovp is triggered. under voltage protection (uvp) both core/gfx vr implement under voltage protection (uvp). if isenxn is less than v refx by 300mv + v offset , vr will trigger uvp latch. the uvp latch will turn off both high side and low side mosfets. when uvp is triggered by one of the vrs, the other vr will enter into soft shutdown sequence. the uvp mechanism is masked when vrx_ready = low. (32) in out min on ripple(max) vv lt i ? = where t on is the ugate turn on period. higher inductance induces less ripple current and hence higher efficiency. however, the tradeoff is a slower transient response of the power stage to load transients. this might increase the need for more output capacitors, thus driving up the cost. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the core must be large enough not to be saturated at the peak inductor current. output capacitor selection output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. usually, the cpu manufacturer recommends a capacitor configuration. two different kinds of output capacitors can be found, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. latter ones are for mid-frequency decoupling with very small esr and esl values while the bulk capacitors have to provide enough stored energy to overcome the low-frequency bandwidth gap between the regulator and the cpu. layout considerations careful pc board layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all of the power components on the top side of the board with their ground terminals flushed against one another. follow these guidelines for optimum pc board layout : under voltage lock out (uvlo) during normal operation, if the voltage at the vcc pin drops below uvlo falling edge threshold, both vr will trigger uvlo. the uvlo protection forces all high side mosfets and low side mosfets off to turn off. inductor selection the switching frequency and ripple current determine the inductor value as follows :
RT8167A 39 ds8167a-00 january 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ` keep the high current paths short, especially at the ground terminals. ` keep the power traces and load connections short. this is essential for high efficiency. ` when trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharging path. ` place the current sense component close to the controller. isenxp and isenxn connections for current limit and voltage positioning must be made using kelvin sense connections to guarantee the current sense accuracy. the pcb trace from the sense nodes should be parallel to the controller. ` route high-speed switching nodes away from sensitive analog areas (compx, fbx, isenxp, isenxn, etc...) ` special attention should be paid in placing the dcr current sensing components. the dcr current sensing capacitor and resistors must be placed close to the controller. ` the capacitor connected to the isen1n/isenan for noise decoupling is optional and it should also be placed close to the isen1n/isenan pin. ` the ntc thermistor should be placed physically close to the inductor for better dcr thermal compensation.
RT8167A 40 ds8167a-00 january 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 5.950 6.050 0.234 0.238 d2 4.250 4.350 0.167 0.171 e 5.950 6.050 0.234 0.238 e2 4.250 4.350 0.167 0.171 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 48l qfn 6x6 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options

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